AI Chips
How training and inference silicon, accelerators and on-device NPUs get chosen, and how capacity, supply and export rules shape delivery timelines.
How training and inference silicon, accelerators and on-device NPUs get chosen, and how capacity, supply and export rules shape delivery timelines.
TorchNeuron is a native PyTorch backend that AWS built for its own AI chips, Trainium. On October 19, 2026, the official PyTorch blog introduced the o...
The first phase of Meta's Prometheus supercluster is complete. On October 19, 2026, Meta disclosed in a post on its official engineering blog that the...
The Shuguang 8000 appeared in physical form on October 17, 2026 at HPC China 2026, the CCF National Conference on High Performance Computing, which op...
NVIDIA and Mercedes-Benz are extending their automated-driving partnership into the next decade. In an announcement published by NVIDIA's newsroom on ...
The inference optimization of Kimi K3 on AMD Instinct MI355X is the result published in a technical post-mortem on vLLM's official blog on October 16,...
NVIDIA used SEMICON West on October 14, 2026 to announce cuPotential, a new library in its CUDA-X family, alongside word that Applied Materials, Caden...
Scimplify's raise sits on a clear backdrop: manufacturers want sources for critical materials outside China. On October 14, 2026, TechCrunch reported ...
Before RTX Spark laptops go on sale, NVIDIA is handing over the software list first. On October 13, 2026, NVIDIA announced on its official blog that t...